TO3: A Compact and Efficient Encoding Scheme for Skewed Slicing Floorplans in VLSI Design

Abstract

A slicing floorplan is a recursive process of drawing a floorplan horizontally and vertically until all the blocks are accommodate into it. In the nanometer era, the escalating transistor density in VLSI chips underscores the necessity of designing compact floorplan representations for VLSI circuits. The paper introduces a novel approach, employing a tree of order three (TO3) for the effective coding of a skewed slicing tree that corresponds to a slicing floorplan. The key innovation lies in the utilization of a TO3 structure, which adds a distinctive dimension to the encoding scheme. The proposed encoding method for a skewed slicing tree achieves a notable reduction in code size compared to previous approaches. Experimental findings from the MCNC benchmark and artificial circuits indicate that the proposed code uses, on average, almost 80% fewer bits than Breadth First code (BFS), 46% fewer than Slicing Pair (SP) code, and 49% fewer than Improved Slicing Pair (ISP) code for encoding a slicing tree, while also reducing CPU running time through a more compact representation of the electronics modules.