Area and Power Efficient Sparse Aware Architecture for Pointwise Convolution Unit using Variable Density Bound Block

Abstract

MobileNet introduced depthwise separable convolution, significantly reducing computations in comparison to standard convolution, making them fit for edge computing. Parameter-efficient models like MobileNet-v1 can be pruned to further reduce the number of parameters. In most of the pruning methods, pointwise convolutional parameters are pruned as they are large in number and depthwise convolutional parameters are kept dense. The efficacy of MobileNet pruning for edge deployment depends critically on a sparsity-aware execution environment. This paper focuses on implementing sparse aware pointwise convolution unit that leverage weight sparsity using Variable Density Bound Block (VDBB) technique. The activation stationary method is also incorporated, as it saves the power to fetch activations continuously. The proposed architecture is implemented on the FPGA platform using Vivado 2024.1. Implementing the sparse-aware architecture on the xc7z045ffv900-1 FPGA resulted in a 358mW reduction in power, a 50% reduction in DSPs, and a 24.06% reduction in LUTs compared to the sparse-unaware architecture. An engine from the proposed architecture was synthesized in ASIC using the TSMC 90 nm standard cell library, resulting in a 30.87% reduction in power and a 32.89% reduction in area when compared to a sparse unaware engine.